//=========================================================================
//    COPYRIGHT(C) Innobeam
//    ALL RIGHTS RESERVED
//=========================================================================
//Filename    : lan9252.v rev 1.0
//Created On  : 2017-09-12
//Author      : shilong.zhang
//Description :use(ivAddrSel)to sellect Direct register,CSR,PRAM
//             3 modes
//
//Include     : lan9252_interface module
//                lan9252csr_proc module
//                lan9252pram_proc module
//
//Modification:
//=========================================================================
module lan9252
(
	iClk 			,//clock input
	iRst_n     		,//input reset,active low

	ivAddrSel 		,//2bit address for sellect operation mode

	//to other modules (TR_control)
	ivAddr 			,//16bit address to lan9252 ESC
	ivData 			,//32bit data input to  lan9252 ESC
	iWrEn			,//input,write enable signal
	iRdEn			,//input read enable signal
	ovData			,//32bit output data
	oDone 			,//output operation is done
	oReady     		,//initilize is done,next operation is ready
	ivNum_pram		,//4bit input Rx/Tx dword number in PRAM mode

	//to PRAM data receive module
	ovData_pram 	,//32bit output pram data;
	ovDpramAddrRx 	,//4bit Pram to dpram address
	oWenDpram		,//output pram write enable

	//to PRAM data transmission module
	ivData_pram 	,//32bit input pram data;
	ovDpramAddrTx 	,//4bit Pram to dpram address
	oRenDpram		,//output pram read enable

	//to extern LAN9252 chip(HBI bus)
	oLan9252AleL 	,//output,LAN9252 ALELO(low address lock enable)
	oLan9252AleH	,//output,LAN9252 ALEHI(high address lock enable)
	oLan9252Cs		,//output,LAN9252 cs(chip sellect)
	oLan9252Rd		, //output,LAN9252 rd(read enable)
	oLan9252Wr		,//output,LAN9252 wr(write enable)
	ivLan9252Ad 	,//input,LAN9252 ad (16bit address and data bus)
	ovLan9252Ad 	//output,LAN9252 ad (16bit address and data bus)
);

//=================================================================================
//    parameter
//=================================================================================
parameter	DATA_W = 16;

//=================================================================================
//    port
//=================================================================================
input 					iClk,iRst_n;

input	[1:0]			ivAddrSel;

input	[DATA_W-1:0]	ivAddr;
input	[2*DATA_W-1:0]	ivData;
input 					iWrEn,iRdEn;
output	[2*DATA_W-1:0]	ovData;
output 					oDone;
output					oReady;

input	[3:0]			ivNum_pram;
output	[2*DATA_W-1:0]	ovData_pram; 	//32bit output pram data;
input	[2*DATA_W-1:0]	ivData_pram; 	//32bit input pram data;
output	[3:0]			ovDpramAddrTx; 	//10bit Pram to dpram address
output	[3:0]			ovDpramAddrRx; 	//10bit Pram to dpram address
output					oRenDpram;
output					oWenDpram;

//to extern LAN9252 chip(HBI bus)
output 					oLan9252AleL,oLan9252AleH,oLan9252Cs,oLan9252Rd,oLan9252Wr;
input	[DATA_W-1:0]	ivLan9252Ad;
output	[DATA_W-1:0]	ovLan9252Ad;

//=================================================================================
//    signal
//=================================================================================
wire					wWr_lan,wRd_lan;
wire	[DATA_W-1:0]	wvAddr_lan,wvAddr_csr,wvAddr_pram;
wire	[2*DATA_W-1:0]	ovData,wvData_lan,wv2Data_csr;
wire					wWr_csr,wRd_csr,wWr_pram,wRd_pram;
wire					oDone;

wire	[2*DATA_W-1:0]	wvRData_lan,ovLanData_csr,wvFData_csr,ovLanData_pram;
wire	[DATA_W-1:0]	ovLanAddr_csr,ovLanAddr_pram;
wire					wdone_lan,wDone_csr,wDone_pram;
wire					oLanWr_csr,oLanRd_csr;
wire	[3:0]			ovDpramAddrTx,ovDpramAddrRx;
wire					oLanWr_pram,oLanRd_pram;
wire	[15:0] 			wvAddr_ini;
wire					oReady_ini,oReady_pram;
wire					oRdEn_ini;

//=================================================================================
//    module body
//=================================================================================

// generate the basic read and write sequence
lan9252_interface i1
(
	.iClk	(iClk),		//50Mhz(LAN9252 RD and WR need 2iClks)
	.iRst_n	(iRst_n),

	// to LAN9252 protocol(normal,csr,pram,router)
	.ivAddr	(wvAddr_lan),
	.iWrEn	(wWr_lan),
	.ivData	(wvData_lan),	// write data to LAN9252
	.iRdEn	(wRd_lan),
	.ovData	(wvRData_lan),	// read data from LAN9252
	.oDone	(wdone_lan),	// operation is done

	// to extern LAN9252 chip(HBI bus)
	.oLan9252AleL	(oLan9252AleL),	// output,LAN9252 ALELO
	.oLan9252AleH	(oLan9252AleH),	// output,LAN9252 ALEHI
	.oLan9252Cs		(oLan9252Cs),	// output,LAN9252 cs
	.oLan9252Rd		(oLan9252Rd),	// output,LAN9252 rd
	.oLan9252Wr		(oLan9252Wr),	// output,LAN9252 wr
	.ivLan9252Ad	(ivLan9252Ad),	// input,LAN9252 ad
	.ovLan9252Ad	(ovLan9252Ad)	// output,LAN9252 ad
);

// generate the CSR read and write sequence
lan9252csr_proc i2
(
	.iClk	(iClk),		//50Mhz(LAN9252 RD and WR need 2 iClks)
	.iRst_n	(iRst_n),

	.ivData	(wv2Data_csr),	//32bit input data
	.ivAddr	(wvAddr_csr),	//16bit input address
	.iWrEn	(wWr_csr),		//write iClk
	.iRdEn	(wRd_csr),		//read iClk
	.ovData	(wvFData_csr),
	.oDone	(wDone_csr),

	// lan9252_interface module interface
	.ovLanData	(ovLanData_csr),	//32bit data to lan9252_interface module
	.ovLanAddr	(ovLanAddr_csr),	//16bit address to lan9252_interface module
	.ivLanData	(wvRData_lan),		//32bit data from lan9252_interface module
	.oLanWr		(oLanWr_csr),
	.oLanRd		(oLanRd_csr),
	.iLanDone	(wdone_lan)
	);

// generate the pram read and write sequence
lan9252pram_proc i3
(
	.iClk	(iClk),		//50Mhz(LAN9252 RD and WR need 2 iClks)
	.iRst_n	(iRst_n),

	.iWrite	(wWr_pram),		//input,enable read and writes to LAN9252 once
	.iRead	(wRd_pram),
	.ivNum	(ivNum_pram),	//10bit input Rx dword number
	.ivAddr	(wvAddr_pram),	//16bit input address
	.oDone	(wDone_pram),
	.oReady	(oReady_pram),

	.ivData			(ivData_pram),		//32bit data from Tx dual port ram data
	.ovDpramAddrTx	(ovDpramAddrTx),	//10bit to Tx dual port ram address
	.oRenDpram		(oRenDpram),		//to Tx dual port ram Read Enable

	.ovData			(ovData_pram),		//32bit data to Rx dual port ram data
	.oWenDpram		(oWenDpram),		//to Rx dual port ram write enable
	.ovDpramAddrRx	(ovDpramAddrRx),	//10bit to Rx dual port ram address

	//lan9252_interface module interface
	.ovLanData	(ovLanData_pram),	//32bit data to lan9252_interface module
	.ovLanAddr	(ovLanAddr_pram),	//16bit address to lan9252_interface module
	.ivLanData	(wvRData_lan),		//32bit data from lan9252_interface module
	.oLanWr		(oLanWr_pram),
	.oLanRd		(oLanRd_pram),
	.iLanDone	(wdone_lan)

);

// give the signal that weather LAN9252 chip initialization is done
lan9252_ini i4
(
	.iClk	(iClk),
	.iRst_n	(iRst_n),
	.ivData	(wvRData_lan),
	.iDone	(wdone_lan),
	.ovAddr	(wvAddr_ini),
	.oRdEn	(oRdEn_ini),
	.oReady	(oReady_ini)
);

// router protocol
router i5
(
	.iClk		(iClk),
	.iRst_n		(iRst_n),

	//comman input sellect signal
	.ivAddrSel		(ivAddrSel),	//input 2bit lan9252 working mode sellect signal

	//normal mode input
	.iReady_ini		(oReady_ini),	//input ready signal from lan9252_ini module
	.iRdEn_ini		(oRdEn_ini),	//input read enable from lan9252_ini module
	.ivAddr_ini		(wvAddr_ini),	//input address 16bit signal from lan9252_ini module
	.ivRData_lan	(wvRData_lan),	//input data 32bit from lan9252_interface module
	.idone_lan		(wdone_lan),	//input done signal from lan9252_interface module
	.ivData			(ivData),		//input data 32bit from lan9252 module extern
	.ivAddr			(ivAddr),		//input address 16bit from lan9252 module extern
	.iWrEn			(iWrEn),		//input write enable from lan9252 module extern
	.iRdEn			(iRdEn),		//input read enable from lan9252 module extern

	//csr mode input
	.ivFData_csr	(wvFData_csr),		//input CSR read in data 32bit from lan9252csr_proc module
	.iDone_csr		(wDone_csr),		//input done signal from lan9252csr_proc module
	.iLanWr_csr		(oLanWr_csr),		//input write enable from lan9252csr_proc module
	.iLanRd_csr		(oLanRd_csr),		//input read enable from lan9252csr_proc module
	.ivLanData_csr	(ovLanData_csr),	//input CSR to lan9252_interface data,from lan9252csr_proc module
	.ivLanAddr_csr	(ovLanAddr_csr),	//input CSR to lan9252_interface address,from lan9252csr_proc module

	//pram mode input
	.iDone_pram		(wDone_pram),		//input done signal from lan9252pram_proc module
	.iLanWr_pram	(oLanWr_pram),		//input write enable from lan9252pram_proc module
	.iLanRd_pram	(oLanRd_pram),		//input read enable from lan9252pram_proc module
	.ivLanData_pram	(ovLanData_pram),	//input PRAM to lan9252_interface data,from lan9252pram_proc module
	.ivLanAddr_pram	(ovLanAddr_pram),	//input PRAM to lan9252_interface address,from lan9252pram_proc module
	.iReady_pram	(oReady_pram),		//input ready signal,from lan9252pram_proc module

	//output to lan_interface
	.oWr_lan		(wWr_lan),		//output write enable to lan9252_interface
	.oRd_lan		(wRd_lan),		//output read enable to lan9252_interface
	.ovData_lan		(wvData_lan),	//output 32bit write data to lan9252_interface
	.ovAddr_lan		(wvAddr_lan),	//output 16bit address to lan9252_interface
	.ovData			(ovData),		//output 32bit data read from CSR or common reg
	.oDone			(oDone),		//output done signal from CSR PRAM or common reg

	.oWr_csr		(wWr_csr),		//output write enable to lan9252csr_proc
	.oRd_csr		(wRd_csr),		//output read enable to lan9252csr_proc
	.ov2Data_csr	(wv2Data_csr),	//output 32bit data to be written to lan9252csr_proc
	.ovAddr_csr		(wvAddr_csr),	//output 16bit address,destination address to lan9252csr_proc

	.oWr_pram		(wWr_pram),		//output write enable to lan9252pram_proc
	.oRd_pram		(wRd_pram),		//output read enable to lan9252pram_proc
	.ovAddr_pram	(wvAddr_pram),	//output 16bit address,destination address to lan9252pram_proc

	.oReady			(oReady)		//output ready signal to lan9252 module extern
);

endmodule

